PLLM:锁相环法
“锁相环法”的英文全称为“Phase Locked Loop Method”,在技术文档和工程实践中,为方便书写与交流,常将其缩写为PLLM。该方法在电子工程、通信系统等综合领域中有广泛应用,尤其在频率合成和信号同步方面发挥着重要作用,属于未明确归类的通用技术方案之一。
Phase Locked Loop Method具体释义
Phase Locked Loop Method的英文发音
例句
- Phase measuring method of filling pulse is studied. While combining frequency-mixing technique of phase locked loop and pulse-filling method, phase demodulation for the heterodyne signal of middle and high frequency is realized.
- 研究了脉冲填充测量相位的方法,同时把锁相环混频降频技术与脉冲填充法结合起来,实现了中高频外差信号的相位解调,拓展了外差信号的处理技术。
- The analysis of APF control strategy, highlights the principles of signal generator and phase locked loop, harmonic separation method and concrete realization of FFT, adaptive control and parameters self regulation functions, principles of output current regulator controlled by direct pulse width.
- APF控制策略分析,重点介绍了信号发生器及锁相环的原理,FFT的谐波分离方法与具体实现,自适应控制与参数自整定功能,直接脉宽控制的输出电流调节器的原理。
- Considering the two facts, this paper comes up with a new method of random number generator based on the noise source of Phase Locked Loop ( PLL ). The method can provide good properties : true randomness and easy to realization and system integration.
- 鉴于这两个现实状况,本文提出了一种基于锁相环噪声源的随机数发生器实现方法,该方法具有真随机性,易于实现和系统集成。
- The key technologies for extracting rotor position are also described, such as delay circuit, synchronous frame filter ( SFF ), and phase locked loop ( PLL ) based on heterodyne method, then make compensation for the rotor poles.
- 随后对转子位置信息提取的关键技术进行了详细介绍,即延时电路,同步轴系高通滤波器及基于外差算法的锁相环电路等。
- Utilizing phase locked loop technique with complex programmable logic devices ( CPLD ), a method to perform high-speed data acquisition, storage and transmission for transformer testing, which solves the problem of data acquisition for high frequency band, is proposed.
- 提出了利用锁相环技术结合复杂可编程逻辑器件(CPLD)实现对变压器测试信号的高速采集、存储、传输的方法,很好地解决了对变压器高频特性信号的采集。
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